The susceptability of integrated circuit memories to soft error or single event upset (SEU) is of particular concern in space. See E. G. Muller, M. S. Gussenhower, K. A. Lynch and D. H. Brenteger, "DMSP Dosimetry Data: A Space Measurement and Mapping of Upset Causing Phenomena". IEEE Trans. Nuclear Science NS-34, pp. 1251-1255 (1987) and H. T. Weaver, et al., "An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM", IEEE Trans. Nuclear Science, NS-34, pp. 1281-1286 (1987). A soft error or single event upset typically is caused by electron-hole pairs created by, and along the path of, a single energetic particle as it passes through an integrated circuit, such as a memory. Should the energetic particle generate the critical charge in the critical volume of a memory cell, then the logic state of the memory is upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the memory cell. The critical charge may also enter the memory through direct ionization from cosmic rays. See T. C. May and M. H. Woods, "Alpha Particle Induced Soft Errors in Dynamic Memories", IEEE Trans. Electronic Devices, ED-26, p. 2 (1979) and J. C. Pickel, J. T. Blaudfood, Jr., "CMOS RAM Cosmic Ray Induced Error Rate Analysis" IEEE Trans. on Nuclear Science, Vol. NS-28, pp. 3962-3967 (1981). Alternatively, the critical charge may result from alpha particles (helium nuclei). One example of SEU can be seen in FIG. 1a which illustrates a cross-sectional view of a CMOS inverter. When alpha particle p strikes bulk semiconductor material in p-channel MOS transistor Pch, it generates electron-hole pairs as shown by the respective minus and plus marks. Assuming that n-channel transistor Nch is on and that p-channel transistor Pch is off, the holes (represented by + signs) which collect (see arrows toward drain D) at drain D can change the voltage at output OUT from a logic low to a logic high. The electrons as indicated by the minus signs will diffuse toward circuit supply voltage Vcc. A charge generating energetic particle hit on transistor Nch has the opposite effect with positive charges drifting towards ground and negative charges collecting at output OUT, thus possibly changing the logic state of the inverter with its n-channel transistor off and its p-channel transistor on.
Further background follows with reference to FIG. 1b which illustrates a schematic drawing of a conventional CMOS (complementary metal oxide semiconductor) static memory cell, typically used in a static random access memory (SRAM). (Note that the term metal used in the pharse metal oxide semiconductor is interpreted in semiconductor and related arts as also encompassing polycrystalline semiconductor material.) Memory cell 2 is constructed according to well known methods of cross-coupled inverter realization and thus CMOS inverters are used in memory cell 2. A first CMOS inverter 4 in memory cell 2 comprises p-channel transistor 6 and n-channel transistor 8 having their source-to-drain paths connected in series between voltage Vcc and ground, and having their gates tied together. The second CMOS inverter 5 in memory cell 2 is similarly constructed, with p-channel transistor 10 and n-channel transistor 12 having their source-to-drain paths connected in series between Vcc and ground and their gates also common. The cross-coupling is accomplished by the gates of transistors 6 and 8 being connected to the drains of transistors 10 and 12 (node S1 of FIG. 1b), and by the gates of transistors 10 and 12 being connected to the drains of transistors 6 and 8 (node S2 of FIG. 1b). N-channel pass transistor 14 has its source-to-drain path connected between node S2 and a first bit line BL, and has its gate connected to word line WL. N-channel pass transistor 16 similarly has its source-to-drain path connected between node S1 and a second bit line BL.sub.--, and has its gate also connected to word line WL. Pass transistors 14, 16 when enabled, allow data to pass into and out of memory cell 2 from bit lines BL and BL.sub.-- respectively. Bit lines BL and BL.sub.-- carry data into and out of memory cell 2. Pass transistors 14, 16 are enabled by word line WL which is a function of the row address in an SRAM. The row address is decoded by a row decoder in the SRAM such that one out of n word lines is enabled, where n is the number of rows of memory cells in the memory, which is a function of memory density and architecture.
In operation, the voltages of node S1 and S2 will necessarily be logical complements of one another, due to the cross-coupled nature of CMOS inverters 4, 5 within memory cell 2. When word line WL is energized by the row decoder (not shown), according to the row address received at address inputs to an address buffer (not shown) connected to the row decoder, pass transistors 14 and 16 will be turned on, coupling nodes S1 and S2 to bit lines BL.sub.-- and BL, respectively. Accordingly, when word line WL is high, the state of memory cell 2 can establish a differential voltage on BL and BL.sub.--. Alternatively, peripheral circuitry forcing a voltage on BL and BL.sub.-- can alter the state of memory cell 2. The sizes of the transistors shown in FIG. 1b are generally chosen such that when pass transistors 14 and 16 are turned on by word line WL; a differentially low voltage at bit line BL with respect to node S2 can force node S2 to a logic low level; and a differentially low voltage at bit line BL.sub.-- with respect to node S1 can force node S1 to a logic low level. However, the sizes of the transistors shown in FIG. 1 are also chosen such that when transistors 14 and 16 are on; a differentially high voltage at bit line BL with respect to node S2 will not force node S2 high; nor will differentially high voltage at bit line BL.sub.-- with respect to node S1 force node S1 high. Therefore writing into memory cell 2 is accomplished by pulling the desired bit line and thus the desired side of cell 2 at either node S1 or node S2 low, which in turn due to feedback paths in cell 2, causes the opposite side of cell 2 to have a logic high state.
One method for hardening a memory cell against SEU is by reducing the amount of charge generated by a given event. This is accomplished for example, by using a silicon film thinner than the collection depth in bulk material. For instance, a memory cell created on a thin film of semiconductor, such as in an SOI (silicon on insulator) device, is less susceptible to SEU than one created on bulk semiconductor, such as silicon, because ionization charge along a path in an insulator is more likely to recombine than be collected compared to ionization charge created in a semiconductor.
Another way to reduce the susceptibility of a memory cell to upset is by increasing the critical charge of the cell.
A hardening scheme against SEU in static memory cells based on increasing the critical charge required to produce SEU is illustrated in the schematic drawing of FIG. 2a. As shown, resistors 18 and 20 are included in the cross-coupling lines of inverters 4 and 5 and they increase the RC time constant delay associated with the gate capacitances of transistors 6, 8, 10, and 12. The initial effect of an energetic particle strike in a critical volume is to change the voltage of one node of the memory cell, say node S1. Upset will occur if this change in voltage propagates through the cross coupling of inverters 4 and 5 before the initial voltage of node S1 is restored. The increased RC delay slows the feedback propagation through the cross coupling and allows more time for recovery of the initially affected node. However, this increase in RC propagation delay also slows the write cycle time of cell 2. The write cycle of a static memory cell in a static random access memory (SRAM) has typically been faster than the read cycle so that some slowing of the write cycle has been acceptable, since the read cycle time was the most critical. However, with scaling of memory cells to small geometries, the speed of the write cycle of SEU hardened cells has become critical. Weaver, op. cit. introduced resistors R1 and R2 to protect against hits on the p-channel transistors 6 and 10 of his inverters as shown in the schematic drawing of FIG. 2b which illustrates the Weaver SEU reduction scheme. However, resistors R3 and R4 are still needed to protect against hits on n-channel transistors 8 and 12, thus limiting the WRITE speed of Weaver's memory cell. Therefore, this resistive approach to SEU hardening is no longer desirable.
Another hardening scheme against SEU based on increasing the critical charge is to increase the capacitance on the inverter drains, thus decreasing the voltage change on the node for a given amount of collected charge. The effectiveness of the capacitance in increasing the critical charge for SEU is increased by having the capacitance between the drains of the two inverters, which, with the cross coupling, is the same as between the gate and drain of the same inverter, as shown in FIG. 2c. FIG. 2c illustrates the same circuit schematic as FIG. 1b with the exception that capacitor 21 is connected across the drains of the transistors of inverters S1 and S2. By having the capacitance between the gate and drain of the inverter, the effect of the capacitance is increased by Miller capacitance. Also, with the capacitance from gate to drain, a change in the drain voltage induces a change in the gate voltage such that the restoring current is increased. Increased capacitance o the gate will also increase the RC delay in the feed back path, thus increasing resistance to SEU and also slowing the write; however, so long as the resistance in the cross-coupling is small, this effect will be minimal. Thus, capacitor 21 can reduce the rate of SEU. However, two constraints must be met. First, capacitor 21 must be small in size in order to meet small circuit geometry requirements. Second, the capacitance of capacitor 21 must be maintained at a certain level in order to insure sufficient SEU hardening. As the level of memory density increases, the need is ever heightened for increased capacitance within the small circuit geometry constraint.